Maria Dominic Savio, M, Anudeep Bonasu, Sanjeevan Goswami, and K N S Reshma. “Low Power Clock Gated Delay Buffers”.
International Journal of Engineering and Technology 7, no. 3.34 (September 1, 2018): 882–884. Accessed May 29, 2025.
https://mail.sciencepubco.com/index.php/IJET/article/view/19581.