Ragavendran, U, M Ramachandran, and . . “Low Power and Low Area Junction-Less Tunnel FET Design”. International Journal of Engineering and Technology 7, no. 3.1 (August 4, 2018): 155–157. Accessed August 17, 2025. https://mail.sciencepubco.com/index.php/IJET/article/view/17076.