SARAVANAKUMAR, U.; SURESH, P; VIMAL, S.P. Low-power, low-latency transceiver design using d-TGMS flip-flop for on-chip interconnects. International Journal of Engineering and Technology, [S. l.], v. 7, n. 1, p. 106–109, 2018. DOI: 10.14419/ijet.v7i1.8730. Disponível em: https://mail.sciencepubco.com/index.php/IJET/article/view/8730.. Acesso em: 13 may. 2025.