Design of Power Efficient 32-Bit Processing Unit - Asha Devi, Dharmavaram; Sandeep, Chintala; Sugun L, Sai (International Journal of Engineering and Technology, 2018)
The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit.Â  The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these frequencies, power analysis is verified for different I/O standards LVCMOS12, LVCMOS25 and LVCMOS33.Â Â