Design and FPGA Implementation of Digital Down Converter for LTE-SDR Receiver - Telagathoti, Pitchaiah; Aparna, Moparthi; Sridevi, P V (International Journal of Engineering and Technology, 2018)
Due to huge demand for high data rate transmission, there is requirement for efficient design of Digital Down Converter (DDC) in wireless communications. DDC is an indispensable part in modern communication, as for higher frequencies it is difficult to down convert the frequency directly to the baseband frequency. Hence a super heterodyne receiver is used to convert the received signal into an intermediate frequency and the intermediate frequency is then converted into the baseband frequency. The architecture of DDC mainly consists of two parts; first one is demodulation and second one is decimation system. The first stage performs the demodulation and the second stage decimation system performs the operation of filtering and decimation. This paper discusses the design and FPGA implementation of DDC for the LTE-SDR receiver for band5 in LTE(UMTS) standards. The design and FPGA implementation of DDC for LTE-SDR is developed and tested using SystemVue software and Xilinx ML507 FPGA board. The results show that simulation results and FPGA implementation results are very close to each other, so the designed DDC can be used in real time LTE SDR application with hardware as FPGA for efficient processing of data with minimum number of resources and at higher operating frequency.