Low power multiply accumulate unit based on modified hybrid Han Carlson adder - S, Rakesh; S. Vijula Grace, K. (International Journal of Engineering and Technology, 2019)
The aim of this work is to propose a modified architecture for implementing Multiply Accumulate (MAC) unit which can be used to build a low power Digital Signal Processor (DSP). The method improves the power consumption as well as the power-delay product. The proposed method uses hybrid parallel prefix adder in the multiplier stage and in the adder stage. In the architecture, a Hybrid HanÂ Â Â Â Â Carlson adder with modified pre-processing and post-processing stages (HHCA_MPPS) is used. The units are designed using Verilog Hardware Description Language (HDL) and simulated and synthesized for Artix-7 series Field Programmable Gate Array (FPGA) using Xilinx Vivado Design Suite 2015.2. The analysis showed that the proposed design has significant improvement in the powerÂ Â Â Â Â Â Â Â Â Â Â Â Â consumption and the figure of merit (power-delay product). The MAC unit employing modified hybrid Han Carlson adder gave a power saving of 11.57% and improvement of 9.21% in the power-delay product.Â