Multi core processor for QR decomposition based on FPGA - S. Omran, Safaa; K. Abdul-abbas, Ahmed (International Journal of Engineering and Technology, 2018)
Hardware design of multicore 32-bits processor is implemented to achieve low latency and high throughput QR decomposition (QRD) based on two algorithms which they are Gram Schmidt (GS) and Givens Rotation (GR). The orthogonal matrices are computed using the first core processor by Gram Schmidt algorithm, and the upper triangular matrices are computed using the second core processor by Givens Rotation algorithm. This design of multicore processor can achieve 50M QRD/s throughput for (4 Ã— 4) matrices at running frequency 200 MHz.Â Â