BCD Divider Architecture For High Speed VLSI Application Using Vedic Mathematics - S, Rishabh; K.M, Harshitha; R Kashyap, Prajwal; C V S, Chaitanya; C, Sundaresan (International Journal of Engineering and Technology, 2018)
Power, delay, area and speed are the parameters used to evaluate any processor performanceÂ in digital domain.Â These parameters should be less to get an effective results. In all VLSI architecture, Division operation is always considered to be more complex, time consuming and bulky. Vedic Mathematics gives a new perspective to mathematics. In this paper we have implemented a BCD division architecture using Nikhilam Sutra a formula (sutra) from the vedic mathematics. Here divider has been designed to improve the results of delay using simple algorithms. The proposed designed is modeled in Verilog, simulated and synthesized using Cadence EDA tools. The proposed Vedic BCD divider performed 29.9% faster than the existing method.Â Â