Hardware Design of AES Core with High Throughput and Low Area - Owusu-Ansah Antwi, Alexander; Ryoo, Kwangki (International Journal of Engineering and Technology, 2018)
Background/Objectives:Â The Advanced Encryption Standard is currently the most used algorithm for symmetric encryption. In this paper, we propose a hardware architecture of AES with an improved key generation unit.Methods/Statistical analysis: We employ the use of a four-stage sub-pipelined architecture for encryption and decryption of all standard key sizes (128, 192 and 256 bits) of the Advanced Encryption Standard (AES). The implementation features an LUT-based S-Box as well as on-the-fly key generation. The RTL of the architecture was designed using Verilog HDL and simulated with ModelSim. The verified design was then synthesized in Synopsis Design Compiler with 180nm TSMC cell libraries.Findings: Since the inception of AES, many implementations have been done in both software and hardware. For the purpose of robustness, the hardware implementation is much preferred. However, for area-constrained implementations, it is necessary for designers to present a very small area of the AES algorithm while keeping the AES structure and security unchanged. The proposed compact key generation unit contributed to the small area of 21.3K equivalent NAND2 gates. The S-Box was implemented as a ROM of size 9.152KB. In order to match the encryption/decryption, the on-the-fly also key generation was accordingly made to output round keys every four cycles. With this structure, there was a high average throughput yield of 11.51Gb/s, 9.75Gb/s and 8.46Gb/s for the 128-bit, 192-bit and 256-bit key lengths respectively, corresponding to a maximum frequency of 1GHz.Improvements/Applications: In the future, we will investigate more techniques to reduce the area of the S-Box and Mix Column structures. We will implement the design on an SoC system for verification and testing.Â