Implementation of Full Adder Using 5-Input Majority Gate
DOI:
https://doi.org/10.14419/ijet.v7i4.4.19598Keywords:
Full-Adder, Five-Input Majority Gate, Energy Efficient, Verification.Abstract
In this paper full adder was created employing five-input majority gate according to Quantum-Dot Cellular Automata (QCA) innovation. We used the QCA logic in our modified structure to reduce the delay. That report details the structure furthermore investigate associated with QCA dependent 1-bit full adder design for minimal energy purposes. This method permits decreasing energy expenditure, delay, additionally location involving electronic circuits.
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Received date: September 12, 2018
Accepted date: September 12, 2018
Published date: September 15, 2018